This invention relates to networks of discrete and remote information processing systems, and more particularly to an efficient and fault-tolerant means for transmitting data between and among the information processing systems.
In many data processing applications, it is advantageous to utilize a network including information processing systems physically remote from one another. One of the better known applications is a computer aided design network consisting of discrete, autonomous systems located throughout one or more plants or other facilities. Each autonomous system has access to all of the remaining systems, eliminating the need to permanently store all data at each location, and insuring that updates in data at any of the systems are substantially immediately reflected in the remaining systems.
The need for such networks arises particularly in environments where certain functions are critical in the sense that failure would result in substantial harm or disruption. Examples include patient monitoring and treatment systems in hospitals, aviation and defense systems, and record management systems in financial institutions. Such systems require a high degree of redundancy, not only in providing alternative paths for data transmission but in providing alternative "back up" processing devices and the ability to rapidly switch operations or functions from one processor to another.
Networks of interconnected systems are known in the art. For example, U.S. Pat. No. 4,564,900 (Smitt) discloses a multiprocessor computer system including a plurality of central processing unit systems connected to one another via an intermemory communication network. The network includes a core designed to cooperate with three satellite systems including device controllers, central processing units and intermemory communication links. Busses in the memory are configured to allow direct data transfer between common memory shared by at least two of the central processing unit systems, without interfering with the central processing units.
This system, while useful in certain environments, does not adequately address the needs of networks including physically remote information processing systems. For transmitting data over the relatively long distances between individual processing systems of a network, fiber optic lines are preferred, as they are virtually immune to interference from outside sources. However, fiber optic lines transmit data serially, giving rise to the need to convert data from its parallel, digital form at the various systems, to serial and optical form for transmission to other systems. Thus, a substantially greater number of components is required to complete the linkage among systems, dramatically increasing the probability of failure of one of the many components of the linkage.
One known approach in this situation is to provide one or more redundant paths, available for transmitting data in the event of a failure along the original path. One such approach is a dual-ring arrangement, for example as disclosed in U.S. Pat. No. 4,837,856 (Glista, Jr.). Glista discloses a fault-tolerant fiber optic coupler/receiver for terminals in a high-speed digital, audio or video data transmission system. Each terminal has one or more bypass lines, and is connected to at least one bypass line from an upstream terminal. Logic on the terminal selects an input from either the primary line or one of the bypass lines, based on predetermined values. A pair of rings is disclosed, both carrying data unidirectionally and in the same direction. U.S. Pat. No. 4,835,763 (Lau) discloses a dual-ring network in which unidirectional rings transmit data in opposite directions. While these arrangements would be expected to perform satisfactorily, their direct application in a network of multiple systems would require multiple point-to-point serial links and excessive electrical loading and circuit card real estate requirements at the processor interface level.
One approach to providing redundancy without point-to-point serial links is disclosed in U.S. Pat. No. 5,081,624 (Beukema), assigned to the assignee of the present application and incorporated herein by reference. More particularly, a fault tolerant connection is provided from a local processing station to several remote processing stations, each including an I/O bus and an associated I/O bus interface logic circuit. Two of the bus interface logic circuits are connected directly to the processor interface circuit, via separate direct links. Intermediate bus interface circuits and I/O busses of the intermediate remote stations are connected between the two directly-connected bus interface circuits, in a series arrangement including alternate link segments and bus interface circuits. Each of the bus interface circuits has pass-through capability for transmitting data in either direction, and the links and link sections also are bidirectional. This enables transmission of data in either direction and on either path between the processor interface circuit and any one of the remote stations. While this interconnection arrangement is successful, there has remained room for further improvements that enhance communications among two or more discrete information processing systems, remote from one another.